1. Technical Field
The present invention relates generally to the data processing field and, more particularly, to a method, system and computer program product for generating effective addresses in a data processing system.
2. Description of Related Art
In a central processing unit (CPU) having an effective address adder for generating effective addresses (EA) which need to be translated, it is important to get the effective addresses to the translation unit as quickly as possible. A CAM (Content-Addressable Memory)-based effective address translation design has been found to perform well, especially in a multi-threaded environment where the utilization of each thread varies dynamically between 0, 50% and 100%. Such a CAM-based effective address translation design, however, requires that all of the bits of the effective address be present at the same time.
One possible approach to generating effective addresses more quickly is to add a cycle into the critical path getting the address to the translation unit. This approach, however, will add a cycle to the cache data valid path, which can be problematic in many designs. Another alternative to generating effective addresses more quickly is to use a translation scheme that does not include a CAM-based translation design. This approach, however, may not provide the overall performance advantages realized by using a CAM-based translation design.
There is, accordingly, a need for a mechanism for generating effective addresses more quickly in a CAM-based effective address translation design.